This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-296076, filed Sep. 28, 2000, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor memory including a ferroelectric gate capacitor structure in which a ferroelectric capacitor is incorporated into the gate structure of a transistor, and a method of fabricating the same.
2. Description of the Related Art
In a semiconductor memory including a ferroelectric gate capacitor structure, a ferroelectric capacitor is formed on a transistor. Since a unit cell has only the area of one transistor, therefore, the structure effectively increases the degree of integration. However, the techniques of fabricating semiconductor memories including a ferroelectric gate capacitor structure still have many problems, so such memories have not been fabricated into products yet.
In the formation of this ferroelectric gate capacitor structure, methods using etching techniques are often used. One example of processes of fabricating semiconductor memories including a conventional ferroelectric gate capacitor structure will be described below with reference to sectional views in FIGS. 40A and 40B.
As shown in FIG. 40A, on the entire surface of a silicon substrate 301 in which a source layer 301a and a drain layer 301b are formed, a 5-nm thick dielectric film 302 made of Bi2SiO5 is formed by CVD or the like. A 10-nm thick Pt film (electrode film) 303 is then formed on the entire surface by using CVD or the like. A 30-nm thick ferroelectric film 304 made of SrBi2Ta2O9 is formed on the entire surface by using CVD or the like. A 10-nm thick Pt film (electrode film) 305 is formed on the entire surface by using CVD or the like.
Subsequently, these dielectric film 302, Pt film 303, ferroelectric film 304, and Pt film 305 are selectively removed by dry etching such as RIE (Reactive Ion Etching) by using an oxide film or a resist 306 as a mask. Consequently, the source layer 301a and the drain layer 301b are partially exposed.
As shown in FIG. 40B, an insulating interlayer 307 is deposited on the entire surface of the device. This insulating interlayer 307 is selectively removed to form trenches 308d to 308f having a predetermined depth. The insulating interlayer 307 is again selectively removed to form a contact hole 308a reaching the source layer 301a, a contact hole 308b reaching the drain layer 301b, and a contact hole 308c reaching the Pt film 305. A metal is deposited in a range including the interiors of the contact holes 308a to 308c and the trenches 308d to 308f. After that, the surface of the device is planarized to expose the insulating interlayer 307. Consequently, contact plugs 311a to 311c and lines 311d to 311f are formed.
If, however, RIE is used as dry etching in the step shown in FIG. 40A, plasma damage or chemical damage happens to the dielectric film 302, the Pt film 303, the ferroelectric film 304, and the Pt film 305. If this dry etching is excessively done, damage also happens to the source layer 301a and the drain layer 301b. 
As described above, the conventional ferroelectric gate capacitor structure formation process readily causes damage. This damage becomes conspicuous as microfabrication advances, leading to a lowering of the reliability.
A ferroelectric capacitor is representatively formed using platinum (Pt) as upper and lower electrodes and a PZT (PbZr1-XTiOX) film as a ferroelectric film. To form an FeRAM by an LSI process using a silicon substrate, the surface of the silicon substrate is covered with an insulating film such as an oxide film. On this insulating film, a lower Pt electrode, PZT film, and upper Pt electrode are formed by patterning, thereby fabricating a ferroelectric capacitor. Usually, a Ti or TiOX film is formed below the lower Pt electrode to improve the adhesion.
In this conventional ferroelectric capacitor, a reducing gas such as hydrogen contained in the Si-LSI process deteriorates the ferroelectric characteristic. More specifically, the spontaneous polarization amount reduces. To prevent this deterioration of the characteristic of a ferroelectric capacitor caused by hydrogen reduction, several countermeasures which prevent invasion of hydrogen and the like into the capacitor have been conventionally proposed. However, none of them is simple and reliable.
In addition to this characteristic deterioration by hydrogen reduction, the characteristics of a ferroelectric capacitor deteriorate by process damage as described earlier. For example, Jpn. Pat. Appln. KOKAI Publication No. 8-335673 discloses a method which, in order to prevent interdiffusion between a ferro-electric capacitor such as PZT and an SiO2 insulating film, covers the ferroelectric capacitor with a diffusion preventing film so that the capacitor and the insulating film do not directly contact each other. This reference describes that TiO2, ZrO2, Al2O3, and the like are effective as the diffusion preventing film. However, the problem in this reference is peeling of the capacitor ferroelectric film by interdiffusion; the reference does not regard deterioration of the ferroelectric capacitor characteristic by hydrogen reduction occurring in the fabrication process as a problem.
Recent research by the present inventors has revealed that using TiOX as an adhesive layer between a ferroelectric capacitor and an SiO2 insulating film brings about several inconveniences. For example, the ferroelectric characteristic deteriorates when Ti diffuses into a PZT film.
According to the first aspect of the present invention, there is provided a semiconductor memory including a ferroelectric gate capacitor structure, comprising
a semiconductor substrate,
a source layer and a drain layer formed in a surface of the substrate, the source layer and the drain layer opposing each other in a channel length direction with a channel region in the surface of the substrate interposed therebetween,
an insulating interlayer formed on the surface of the substrate to extend from the source layer to the drain layer, the insulating interlayer including a hole at a position corresponding to the channel region, and the hole extending across the channel region in the channel length direction,
a capacitor insulating film comprising a ferroelectric film and formed to cover bottom and side surfaces of the hole, the capacitor insulating film including a first recess at a position corresponding to the channel region,
an upper electrode formed to cover bottom and side surfaces of the first recess, and
a dielectric film formed between the substrate and the capacitor insulating film to cover the bottom surface of the hole.
According to the second aspect of the present invention, there is provided a semiconductor memory including a ferroelectric gate capacitor structure, comprising
a semiconductor substrate,
a source layer and a drain layer formed in a surface of the substrate, the source layer and the drain layer opposing each other in a channel length direction with a channel region in the surface of the substrate interposed therebetween,
an insulating interlayer formed on the surface of the substrate to extend from the source layer to the drain layer, the insulating interlayer including a hole at a position corresponding to the channel region, and the hole extending across the channel region in the channel length direction,
a capacitor insulating film comprising a ferroelectric film formed to cover a bottom surface of the hole and contact side surfaces of the hole, and
an upper electrode formed to cover the capacitor insulating film in the hole and contact the side surfaces of the hole,
wherein the capacitor insulating film and the upper electrode have different lengths in the channel length direction, and first and second portions of the hole on the same level as the capacitor insulating film and the upper electrode have different lengths in the channel length direction.
According to the third aspect of the present invention, there is provided a method of fabricating a semiconductor memory including a ferroelectric gate capacitor structure, comprising
forming a source layer and a drain layer in a surface of a semiconductor substrate, the source layer and the drain layer opposing each other in a channel length direction with a channel region in the surface of the substrate interposed therebetween,
forming, on the surface of the substrate, an insulating interlayer extending from the source layer to the drain layer and including a hole at a position corresponding to the channel region, the hole extending across the channel region in the channel length direction,
sequentially stacking a dielectric film, a capacitor insulating film comprising a ferroelectric film, and an upper electrode film on the insulating interlayer to cover bottom and side surfaces of the hole, and
removing portions of the dielectric film, the capacitor insulating film, and the upper electrode film on the insulating interlayer by planarization.
According to the fourth aspect of the present invention, there is provided a method of fabricating a semiconductor memory including a ferroelectric gate capacitor structure, comprising
forming a source layer and a drain layer in a surface of a semiconductor substrate, the source layer and the drain layer opposing each other in a channel length direction with a channel region in the surface of the substrate interposed therebetween,
forming, on or above the surface of the substrate, a first insulating interlayer extending from the source layer to the drain layer and including a first recess at a position corresponding to the channel region,
stacking a capacitor insulating film comprising a ferroelectric film on the first insulating interlayer to cover bottom and side surfaces of the first recess,
removing a portion of the capacitor insulating film on the first insulating interlayer by planarization, thereby leaving the capacitor insulating film in the first recess,
forming, on the first insulating interlayer and the capacitor insulating film, a second insulating interlayer including a second recess at a position corresponding to the channel region and exposing the capacitor insulating film, the first and second recesses having different lengths in the channel length direction,
depositing an upper electrode film on the second insulating interlayer to cover bottom and side surfaces of the second recess, and
removing a portion of the upper electrode film on the second insulating interlayer by planarization.